Design of Ceramic–Capacitor VRM’s with Estimated Load Current Feed forward
Angel V. Peterchev Seth R. Sanders
Department of Electrical Engrineering and Computer Science
University of California, Berkeley, USA
Abstract—
For voltage regulator module (VRM) designs with ceramic output capacitors, the capacitor size has to be chosen sufficiently large to allow for the use of relatively large inductor values. This enables operation at conventional switching frequencies, while meeting load transient response specifications. Due to the small effective series resistance (ESR) time constant of ceramic capacitors, this may result in designs with output capacitor ESR substantially lower than the desired output impedance. This is in contrast to conventional VRM implementations with electrolytic capacitors, where the desired output impedance is closely related to the output capacitor ESR. The feedback bandwidth is limited by stability constraints linked to the switching frequency. The use of load current feedforward can extend the useful bandwidth beyond the limits imposed by feedback stability constraints. Load current feedforward is used to handle the bulk of the regulation action, while feedback is used only to compensate for imperfections of the feedforward and to ensure tight DC regulation. An experimental converter demonstrates tighter output regulation with estimated load current feedforward, than with pure feedback control.
INTRODUCTION
The specifications for modern voltage regulator modules (VRM’s) require that the microprocessor supply voltage Vo follows a load line, Vo = Vref - Rref Io,
where Vref is the reference voltage, Rref is the desired load line slope (or regulator output impedance), and Io is the current drawn by the microprocessor load.
A method for load-line regulation , where the closed-loop output impedance is set equal to the output capacitor effective series resistance (ESR), was introduced. With this approach, the nominal system closed-loop bandwidth is tightly related to the output capacitor ESR time constant. With conventional electrolytic capacitors having such a time constant on the order of 10 µs, it is straightforward for this approach to work with conventional switching frequencies in the range of 200– 500 kHz. For modern VRM applications, ceramic capacitors present an attractive alternative to electrolytics due to their low ESR and low effective series inductance (ESL), better reliability, and low profile. However, ceramic capacitors have ESR time constants of about 0.2 µs, yielding the conventional load-line design framework unworkable, since it would require switching frequency on the order of 10 MHz.
Due to the small ESR time constant of ceramic capacitors, this may result in designs with output capacitor ESR substantially lower than the desired output impedance. This is in contrast to conventional VRM designs with electrolytic capacitors, where the desired output impedance is closely related to the output capacitor ESR. In ceramic capacitor designs with conventional feedback control, the required loop bandwidth is inversely proportional to the output capacitor size. Extending the bandwidth can result in cost and board area savings, since it can reduce the required number of capacitors. However, bandwidth in a feedback-controlled converter is limited by stability constraints linked to the switching frequency.
In this approach, the load current feedforward is used to handle the bulk of the regulation action, while the feedback is used only to compensate for imperfections of the feed forward and to ensure tight DC regulation. unloading current step. Previous derivations of the critical inductance, use assumptions which yield the critical inductance value directly proportional to the output capacitor ESR time constant
tC = rCC, where C is the output capacitance and rC is the ESR.
As a result, these analyses suggest the need for very low critical inductance values for VRM’s using low- ESR ceramic output capacitors, implying, in turn, the need for high switching frequencies. Further, these derivations assume infinite load current slew rates (tI = 0), and no unloading overshoot (?Vp = 0), while VRM specification list finite values (Table I). Here, we present an extended analysis, which reveals a more detailed relation between the critical inductance value and other key power train parameters. Fig. 2 shows a model of the VRM response for a large unloading transient. The unloading current step can be modeled by a magnitude ?Io and a time constant tI which characterizes the slew rate, Io(t) = Io(0) - ?Io(1 - e -t/tI ), (2) for t = 0. The maximum control effort the VRM controller can exert after a large unloading transient, is to saturate the duty ratio to zero after some delay td inherent in a physical implementation. The most important observation is that the critical inductance depends strongly on the output capacitance, rather than on the ESR time constant, when the output impedance is allowed to assume values different from the capacitor ESR. This implies that in ceramic capacitor VRM designs, the output capacitance has to be chosen sufficiently large to allow for a reasonably high inductance value, and thus enable operation at conventional switching frequencies (e.g., < 1 MHz). Due to the small ceramic capacitor ESR time constant, this results in designs where the ESR is smaller than the specified output impedance Rref .
For a design example, consider the critical inductance for the VRM specifications. Assume a 4-phase converter with Vref = 1.3 V, C = 800 µF, tC = 0.2 µs, and td = 100 ns. Then we obtain Li,crit ˜ 318 nH per phase. These power train parameters allow efficient operation with a 1 MHz switching frequency.Further, the critical inductance for the loading transient is approximately 1.58 µH—much larger than Li,crit. This confirms the observation that the unloading transient presents the critical conditions for the transient design.
While the previous section addressed power train design considerations for all-ceramic capacitor VRM’s, here we discuss the appropriate control strategies for regulating the output impedance to meet the specifications. A. Output Impedance Regulation Conventional load-line VRM control sets the desired closedloop impedance equal to the output capacitor ESR . However, the discussion above indicates that in ceramic capacitor VRM designs, the output capacitor ESR may be substantially smaller than Rref , to enable operation at moderate switching frequencies. With this approach the output impedance is specified dynamically, as a generalization of the resistive output impedance specified in conventional load-line control. This behavior is illustrated in Fig. 3. Importantly, the controller has to be designed so that the output impedance is regulated to Zref and not to Rref , since the latter approach will result in undesirable behavior, when during a load transient, the controller initially acts to change the inductor current in direction opposite to the load step, eventually producing additional output voltage overshoot.
Output Current Feed forward It has been shown that for conventional VRM designs with current-mode control, where Rref = rC, the voltageloop bandwidth should be equal to 1/tC rad/s, to ensure appropriate output impedance control. In VRM designs with voltage-mode load-line control the loop bandwidth has to be larger than 1/tC, to provide tight load-line regulation. Since in both cases the feedback controller bandwidth is constrained by the switching frequency for stability reasons, these approaches require very high switching frequencies, on the order of 10 MHz, for ceramic capacitor designs. On the other hand, in the generalized load-line regulation approach discussed here, for Rref = rC, the feedback loop bandwidth should exceed 1 refC, which corresponds to the dominant time constant characterizing the output impedance. Thus, if conventional feedback control is used, the output capacitor should be selected sufficiently large, so that 1 refC is less than the practical feedback loop bandwidth. Clearly, in this case there is a trade-off between the number of output capacitors required and the switching frequency used. To eliminate this constraint, and thus enable operation at moderate switching frequencies (fsw < 1 MHz), with a small number of ceramic capacitors (C < 1 mF), we introduce load current feedforward. Load current feedforward can decrease the converter response time, without an increase of the switching frequency, since the gain and bandwidth of the feed forward are not limited by stability considerations, in contrast to pure feedback regulation. The use of load current feed forward to speed up the load transient response in current-mode converters with stiff voltage regulation, has been demonstrated
The modulation of the feedback signal, however, can possibly cause subharmonic instability resulting from the closed-loop bandwidth approaching relatively near the switching frequency due to the small power train energy storage element values [8]. To prevent this from happening, a sample-and-hold (S/H) operating at the effective switching frequency fsw,eff = fsw of an N-phase converter, could be introduced in the feedback path, thus eliminating switching ripple and reducing the bandwidth of the control signal. The sample-and-hold could be preceded by a resettable integrator ( ) averaging the feedback signal over each effective switching period (1/fsw,eff ), and thus providing good DC accuracy of the feedback control. The sample-and-hold and the resettable integrator would introduce some additional delay in the feedback path, however this is not critical to the overall speed of response since fast load changes are handled by the feed forward path. All of these have turn-off latency equal to or less than the steadystate on-pulse-width, which is about a tenth of the switching period in 12-V VRM’s. Hysteretic modulation also offers very fast response, however its switching frequency is not fixed, and it is difficult to generalize it to multi-phase power trains.
For a design example, consider the critical inductance for the VRM specifications. Assume a 4-phase converter with Vref = 1.3 V, C = 800 µF, tC = 0.2 µs, and td = 100 ns. Then we obtain Li,crit ˜ 318 nH per phase. These power train parameters allow efficient operation with a 1 MHz switching frequency.Further, the critical inductance for the loading transient is approximately 1.58 µH—much larger than Li,crit. This confirms the observation that the unloading transient presents the critical conditions for the transient design.
While the previous section addressed power train design considerations for all-ceramic capacitor VRM’s, here we discuss the appropriate control strategies for regulating the output impedance to meet the specifications. A. Output Impedance Regulation Conventional load-line VRM control sets the desired closedloop impedance equal to the output capacitor ESR . However, the discussion above indicates that in ceramic capacitor VRM designs, the output capacitor ESR may be substantially smaller than Rref , to enable operation at moderate switching frequencies. With this approach the output impedance is specified dynamically, as a generalization of the resistive output impedance specified in conventional load-line control. This behavior is illustrated in Fig. 3. Importantly, the controller has to be designed so that the output impedance is regulated to Zref and not to Rref , since the latter approach will result in undesirable behavior, when during a load transient, the controller initially acts to change the inductor current in direction opposite to the load step, eventually producing additional output voltage overshoot.
Output Current Feed forward It has been shown that for conventional VRM designs with current-mode control, where Rref = rC, the voltageloop bandwidth should be equal to 1/tC rad/s, to ensure appropriate output impedance control. In VRM designs with voltage-mode load-line control the loop bandwidth has to be larger than 1/tC, to provide tight load-line regulation. Since in both cases the feedback controller bandwidth is constrained by the switching frequency for stability reasons, these approaches require very high switching frequencies, on the order of 10 MHz, for ceramic capacitor designs. On the other hand, in the generalized load-line regulation approach discussed here, for Rref = rC, the feedback loop bandwidth should exceed 1 refC, which corresponds to the dominant time constant characterizing the output impedance. Thus, if conventional feedback control is used, the output capacitor should be selected sufficiently large, so that 1 refC is less than the practical feedback loop bandwidth. Clearly, in this case there is a trade-off between the number of output capacitors required and the switching frequency used. To eliminate this constraint, and thus enable operation at moderate switching frequencies (fsw < 1 MHz), with a small number of ceramic capacitors (C < 1 mF), we introduce load current feedforward. Load current feedforward can decrease the converter response time, without an increase of the switching frequency, since the gain and bandwidth of the feed forward are not limited by stability considerations, in contrast to pure feedback regulation. The use of load current feed forward to speed up the load transient response in current-mode converters with stiff voltage regulation, has been demonstrated
The modulation of the feedback signal, however, can possibly cause subharmonic instability resulting from the closed-loop bandwidth approaching relatively near the switching frequency due to the small power train energy storage element values [8]. To prevent this from happening, a sample-and-hold (S/H) operating at the effective switching frequency fsw,eff = fsw of an N-phase converter, could be introduced in the feedback path, thus eliminating switching ripple and reducing the bandwidth of the control signal. The sample-and-hold could be preceded by a resettable integrator ( ) averaging the feedback signal over each effective switching period (1/fsw,eff ), and thus providing good DC accuracy of the feedback control. The sample-and-hold and the resettable integrator would introduce some additional delay in the feedback path, however this is not critical to the overall speed of response since fast load changes are handled by the feed forward path. All of these have turn-off latency equal to or less than the steadystate on-pulse-width, which is about a tenth of the switching period in 12-V VRM’s. Hysteretic modulation also offers very fast response, however its switching frequency is not fixed, and it is difficult to generalize it to multi-phase power trains.
EXPERIMENTAL RESULTS
To test the concepts discussed in this paper, a 1 MHz, 120 A, 4-phase synchronous buck converter board (International Rectifier IRDCiP2002-C) was modified to incorporate estimated load current feed forward and load-line regulation with the controller structure. The on-board voltage mode PWM modulator with phase current balancing (Intersil ISL6558) was used A unloading transient with corresponding estimated load current and output voltage with and without load current feedforward. and unloading transients between 60 A and 112 A. Due to hardware constraints on the pulsed load circuit, the loading current step is relatively slow with a time constant of about 500 ns. The unloading current step, which tests the critical performance of the converter, is much faster.
Estimated load current follows very well the measured current with a delay of about 100 ns. The 4 MHz switching noise present in the load current estimate results from parasitic coupling to the sense wires which were soldered on top of the VRM board. The switching noise does not affect the DC regulation precision because it is attenuated by the PID controller. Further, in a dedicated implementation, the sensing can be done through buried PCB traces, thus reducing both electrostatic and magnetic pickup. From the loading transient in Fig. 7 it can be seen that with combined feedback and feedforward control, the output voltage follows very well the desired load line. With only feedback, however, there is an extra sag of about 40 mV reflecting the inability of the feedback controller to tightly regulate the output impedance. Note that this overshoot is due to bandwidth limitations of the feedback controller, since the feedback loop crossover frequency is not significantly larger than 1 refC, as required in Section III-B. The observed ^ Io 1 us/div Io 10 mV/div Vo Vo 8 A/div 8 A/div feedback only Fig. 9. A 8 A unloading transient with corresponding estimated load current and output voltage with and without load current feedforward. overshoot is not a result of duty ratio saturation, since the phase inductor value is substantially smaller than the critical inductance of 1.58 µH for loading transients, calculated in Section II-A. In the unloading transient in Fig. 8, an extra overshoot of about ?Vp ˜ 85 mV can be observed, which is expected given the prototype parameters listed above. This response corresponds to the duty ratio being saturated to zero about 300 ns after the beginning of the load step. Here too, the combined feedback and feedforward control produces a better voltage response than the feedback alone, implying a faster transition to duty ratio saturation. In implementations using a faster modulator, the advantage of the feed forward scheme is expected to be even greater for large unloading transients, since the duty ratio can be driven to saturation even faster. Finally, Fig. 9 shows a smaller 68-to-60 A unloading transient which does not drive the duty ratio to saturation. Analogously to the loading transient example in Fig. 7, it is clear that the combination of feedback and feedforward provides tighter output impedance regulation than feedback alone.
CONCLUSION
For representative VRM designs with ceramic output capacitors, the capacitor size has to be chosen sufficiently large to allow for the use of inductor values in the range of hundreds of nH, thus enabling efficient operation at conventional submegahertz switching frequencies.For designs with ceramic capacitors, the loop bandwidth required with conventional feedback control, is inversely proportional to the output capacitor size. Extending the bandwidth can result in cost and board area savings, since it can reduce the required number of capacitors. However, bandwidth in a feedback controlled converter is limited by stability constraints linked to the switching frequency. In both current-mode and voltage mode control, load current feedforward can extend the useful bandwidth beyond that achievable with pure feedback, since feedforward is not limited by stability constraints. The load current can be estimated from the inductor and capacitor voltages with simple RC networks. More sophisticated and robust estimation schemes, using the input current, for example, can be developed in the future. Different types of modulators can be used with the load feedforward scheme, as long as they have low latency with respect to unloading transients. The ability of estimated load current feedforward to provide tighter output impedance regulation than that with pure feedback control, was demonstrated with an experimental 12-to-1.3 V, all-ceramic capacitor
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